This talk will present the detailed design and construction of large-scale phased arrays for 60 GHz 5G communications and their use in point-to-point re-configurable networks doing Gbps communications over large distances. To our knowledge, these are the largest phased array developed to date (256 elements) and work will be shown on 512 and 1024 element arrays. Different constellations up to 64QAM will be shown to be transmitted using these phased arrays and with low EVM.

Receiver architectures and circuits for the 5G technologies will be reviewed in this presentation. Two possible architectural directions towards 5G are considered. From the SNR point of view, we can think of the sensitivity radio (or the long-distance radio) as the one extreme, and the maximum throughput radio (or the short-distance radio) as another extreme. From the technology point of view, we can think of the co-working cellular radio (or the 3G/4G/4G+ radio) as the one extreme, and the co-working connectivity-cellular radio (4G+/WLAN radio) as the another extreme. All these cellular and connectivity technologies ‘speak’ different standardization languages, but from the RF IC design point of view there are many similarities that could be used to build a universal radio working across all the SNRs, distances, throughputs, and technologies from the very same circuits. In this presentation, the receiver architectures and circuits meeting this common goal of ‘all-in-1’ radio will be put up for a consideration. An imaginary local very-high throughput personal network (radio-belt) is introduced as a vehicle to build a 5G system with a 10Gb/s data rate. Design trade-offs between different modulation schemes, bandwidths, bands, and MIMO and beamforming signal-processing techniques are discussed throughout the presentation and their impact on the 5G circuit and architecture design outlined.

The 2000s saw the maturation of millimeter-wave silicon systems-on-chip (SoC) for short-range indoor high-data-rate applications. However, over the past few years, we have seen a growing interest in exploiting millimeter-wave spectrum for cellular mobile communications to satisfy the exponential increasing capacity demanded from next-generation (xG) communication networks. What technologies will such applications demand that have not already been demonstrated in silicon? This talk will explore various directions that will be critical for cellular mobile communications - large-scale phased arrays, digital-intensive high-power transmitters as well as some emerging communication paradigms such as full-duplex and MIMO. We will discuss both system aspects as well as RFIC prototypes that exploit novel cross-layer co-design techniques to achieve state-of-the-art performance.

In this presentation, a CMOS millimeter-wave transceiver will be introduced for a 5G cellular communication. To realize 64QAM in a millimeter-wave transceiver, the requirements of RF front-end will be discussed especially about SNDR, image calibration, and phase noise with digitally-assisted calibration techniques.

In China, besides some candidate frequency bands bellow 15 GHz, the millimeter wave frequency bands of 30 GHz, 45 GHz and 80 GHz have also been considered as the candidate frequency bands for 5G wireless communications. In this talk, the research advances in 45GHz bands, including standardization, IC design and demo systems are reviewed.

In this presentation, an efficient beamforming solution operating at 60 GHz enabled by a multi-chip implementation in SiGe BiCMOS technology will be described. The proposed solution is highly compact, and can be expanded in a modular fashion, making it suitable for backhaul communication as well as 5G access and industrial communication scenarios. The architecture makes use of multiple beamforming ICs, consisting of amplifiers and vector modulators, and a separate IQ modem chip which includes up and down converters controlled by an integrated PLL. The architecture can flexibly be adapted to different applications scenarios, as performance parameters can be adjusted through the number of beamforming ICs and panel size. As a final result, a very compact system solution is introduced including the frontend, as well as baseband components and supply generation.

New functionality, higher frequencies and new use cases in 5G Wireless Systems are driving research to solve new challenges. This session will give an overview of 5G in general and new Radio Access technology in particular. Roadmap to commercial service including expected spectrum, standardization milestones, important demo events and targets for commercial introduction will be presented. Usage and examples of applications will also be covered. New features and functionality will be presented. Ericsson 5G test bed development and results of performed trials will be shown.

The exponential increase of mobile data traffic, driven by smartphone and tablets, requires disrupting approaches in the definition of the future 5G network. The trend is to reduce the network cell size and offload a great part of this traffic to small cell access points, optically or wirelessly linked together and backhauled to the core network. In this scope the huge frequency bands available at millimeter wave should be good candidates for opportunistic high data rate data transfer. The latest breakthrough in CMOS and BiCMOS technologies are paving the way for the development of mmW devices at low cost for 5G small cells. Within this talk, an heterogeneous network infrastructure is proposed based on the superimposing of millimeter wave access point and backhaul to the former cellular infrastructure. A focus will be made on the tricky access point architecture and design, through the framework of the H2020 MiWaveS project.

The emerging Internet of Things (IoT) market requires radios that operate with very low average power consumption to support battery life measured in years, or even battery-free operation. At the same time, both low cost and small form factor designs are required to enable large market growth rates and a wide variety of applications. Oscillator calibration is a powerful technique that allows these goals to be met. The radio in an IoT wireless node is typically aggressively duty-cycled to reduce average power consumption, waking only occasionally to send or receive data packets. To synchronize these data packets, a sleep timer is needed, which can be implemented as a low frequency crystal or integrated oscillator. The total system power is then limited by the sleep timer power and frequency stability. Calibration techniques to improve the frequency stability of a low frequency crystal oscillator are described, as well as techniques that allow the low frequency crystal oscillator to be replaced with an integrated oscillator to reduce the solution size. System level calculations will be shown to explain the design tradeoffs involved between energy required for calibration and energy used by the sleep timer itself. The radio synthesizer requires a reference clock which is implemented with a crystal oscillator. In duty cycled systems with short data packet lengths, the crystal oscillator startup time can be a dominant contributor to average power consumption. The startup time can be reduced by injecting another tone from an integrated oscillator into the crystal. Calibration of the integrated oscillator is required for this technique to be effective. Also, the calibration that is performed to optimize frequency, amplitude, and phase noise of the crystal oscillator will be presented.

With the rapid development of wireless communication networks, it is expected that more complex CMOS radios supporting multi-band and multi-mode in 4G mobile systems will appear in the market. In addition, mmWave radio developments for mobile and backhaul applications are also accelerating. The expansion of circuit topologies and architectures that can be easily reconfigured while providing a near optimal trade-off between area, power, and performance trade is a key challenge. On the other side, the ongoing shrink in CMOS technology enables increased functionality in even smaller silicon area. However technology effects, including process and temperature variation, put stringent challenges on the design and have significant impact on the production yield. The objective of this talk is to describe calibration techniques utilized in complex radio for 4G, and then extend to 5G radios. First we discuss the benefit and challenges of designing a multi-band, multi-mode radio. Then, we identify the key parameters and impairments which impose significant design overhead such as area, power, and performance. Next, we review different calibration techniques used to digitally assist the analog and RF blocks to meet the performance with minimum power and area penalty. Among them are: radio frequency response, receiver gain, DC offset, IQ gain and phase imbalance in receiver and transmitter, 2nd order inter-mod., output power, filter corner frequency. In the end, techniques extendable to carrier aggregated radio and 5G systems will be reviewed.

Sub-micron CMOS circuits experience increasing variability between devices and chips as the minimum feature size scales ever lower, necessitating advanced calibration techniques to correct for errors in process variation and temperature (PVT), especially early in a process node’s life cycle. mm-Wave circuits including power amplifiers (PAs) can be especially susceptible to these variations as they are critically dependent on the parameters of the active devices and metal stack. Self-healing is a method that can be used for this calibration by incorporating a digitally assisted feedback loop as a method for correcting for these sources of performance degradation as well as additional challenges posed by load impedance mismatch, transistor aging and modeling inaccuracies. This presentation will explore methods for implementing self-healing loops for calibration of mm-wave integrated circuits that can accurately sense the performance metrics of interest, and takes advantage of the vast computational power of advanced CMOS to correct any performance degradation using control knobs that create a sufficiently large actuation space.

The possibilities of modern CMOS process technology lead to more extensive use of digital assistance for RF circuits. PLLs and especially digital PLLs are well suited for digital assistance as many crucial circuit parameters can be optimized greatly by means of calibration and digital correction mechanisms. This presentation will show techniques for digital assistance in oscillator band search, nonlinearity calibration and correction of modulation errors in phase modulated RF PLLs

In the last 70 years radars evolved from large structures displaced along the southern coasts of England to relatively compact systems that are found today in high and middle range cars. The advancement in CMOS technology allowing operation at mm-Wave frequencies such as 77, 79 GHz or even higher, will further reduce cost and size of these devices in the coming years. Thanks to the capability of accurately measure distance and speed of objects regardless of the ambient light and conditions, mm-wave CMOS radar technology will be a key player in improving road safety and collision avoidance. At the same time low cost and compact mm-wave CMOS radars will be extensively used in industrial environment and robotics, surveillance system, drones, and the smart homes of tomorrow where appliances will actively interact with users.

The wide bandwidths, short wavelength, and diverse material interactions of mm-wave signals offer rich potential for sensing and imaging applications. These applications benefit from arrays of transceivers with high levels of synchronization, small form factor, low power dissipation, and efficient low frequency and RF interfaces. The challenges extend from the gain-limited front-end all the way through the signal processing backend. This talk will explore challenges and some solutions addressing the RF signal path, design methodology, antenna, baseband, timing control, and power management, specifically focusing on a 160GHz pulsed radar transceiver array demonstrator integrated in 65 nm CMOS.

Google’s Project Soli is bringing millimeter-wave radars to everyday use as an inexpensive, robust and rich technology for fine human gesture sensing. Radio frequency waves have several attractive properties for tracking human interaction: the sensors do not depend on lighting, noise or atmospheric conditions; are extremely fast and highly precise; and can work through materials, which allows them to be easily embedded into devices and environments. The novel sensing techniques we developed have enabled us to shrink the physical sensor, including circuitry and antennas, to a single chip, while robustly tracking and recognizing complex, fluid finger gestures at very close range with sub-millimeter accuracy. By capturing the sensitivity and precision of human hand movements in everyday user interfaces, scalable millimeter-wave technology has the potential to revolutionize the way we interact with technology.

In order to make the vision of ubiquitous mmWave systems for sensing and communications a reality, their test must become cost-effective and their calibration efficient in various environment conditions. This is challenging due to the high frequencies involved, increasingly high levels of complexity/integration, close interaction between circuits and packaging/antennas, and the inherent variability of the advanced silicon technologies employed. This presentation will first discuss recently developed techniques for the on-chip test and calibration of key performance metrics such as NF and output power at mmWave frequencies. And end-to-end approach is taken for these methods, considering modeling, statistical simulation, and the design of on-chip sensors and supporting infrastructure. Measurements results from CMOS implementations and in the presence of PVT variations are presented. Finally, this talk will address how these techniques can be applied to packaged transceivers and how they can evolve to ultimately realize mmWave systems with fully autonomic performance calibration/adaptation.

The rapid growth of wireless data drives new design challenges for RF chipset and handheld/mobile device manufacturers along with carriers. The massive data traffic to be supported by wireless networks requires the development of cost effective high speed and low power wireless link (both from end user and network side). To address this challenge, millimeter wave technologies (WiGig standard at 60 GHz, backhauling in E band …) have emerged as promising solutions in order to offer multi gigabit per second data rate at low power. Moreover, the possibility to integrate those wireless systems using silicon based technologies (either CMOS or BiCMOS) enables to offer cost effective solutions required by both consumer and industrial markets (we can have in mind here the cost constraint related to the deployment of 5G heterogonous network). But millimeter wave technologies do not only require cost effective RF ICs achieved in advanced silicon technologies, high performances and low cost packaging and antenna technologies are also key issues. This talk will try to illustrate how industrial organic packaging technology and digital manufacturing (for example 3D printing) technologies can help to develop innovative and cost effective mmw packages and antennas (in the 60 GHz – 140 GHz band) in order to address new wireless businesses challenges.

Channels measurements at mmWave frequencies are of great interest today as the industry is focusing attention to very high frequencies in search for more bandwidth, data rates and capacity. High frequencies 10-100GHz have great promise, but measurements are needed to understand propagation in different settings including indoor and outdoor, offices, urban, micro-urban, residential, shopping malls, etc. Qualcomm Technologies has been at the forefront of these activities and contributed significantly to understanding some unique characteristics of propagation at these high frequencies. Qualcomm Technologies measurements usually includes reference measurements at a low band (

The construction of large phased arrays, composed of 64-256 elements, with relatively low-cost is one of the main problems of 5G systems. In this talk, we will present our effort in this area and show 64-256 element phased arrays operating at 60 GHz. This is done using highly complex and integrated silicon (SiGe) chips, capable of phase shifting and frequency translation functions, and operation up to 100C. Measured patterns and communication links capable of 2 Gbps (802.11ad) over hundreds of meters will be shown.

Cost-effective solutions for millimeter-wave communication and radar systems are emerging nowadays and will impact many sectors, including automotive, industrial and telecom applications. In particular, they will be a key enabler in future mobile networks to boost their capacity through a dense deployment of (small-)cells exploiting millimeter-wave radios for access both backhaul and fronthaul. This talk will focus on high-gain millimeter-wave transmit-array antennas developed in the perspective of current and future backhaul/fronthaul applications. In addition to competitive performances in terms of efficiency, bandwidth, weight and cost, transmit-array antennas offer very interesting opportunities in terms of reconfigurability, enabling innovative functionalities such as fine beam-steering for self-alignment or interference mitigation, or wide angle beam-steering or multi-beam synthesis for point-to-multi-point applications. The presentation will include several examples in Ka, V and E band with state-of-the-art experimental results both from advanced research prototypes and mature industrial prototypes.

Wireless power transmitters convert DC power to AC at a specific operation frequency, but this is only one of many functions required in a standards-compliant transmitter. Power-level modulation, dc and ac current sensing, and in-band signal decoding are also required features, to name a few. Most or all of these features can be integrated into an application-specific IC to reduce the cost and size of the transmitter electronics. We will discuss the key elements of wireless power transmitters and how they can be integrated, comparing and contrasting the implementations across various industry standards. We will further highlight some of the challenges faced by transmitter IC designers in an environment where multiple evolving standards are relevant.

Presentation will discuss the issues and design considerations for implementing a Qi/PMA/A4WP wireless charging receiver. Topics include coils and matching networks, synchronous rectification difficulties, over-voltage protection, efficiency, and EMI considerations.

Wireless power transmission (WPT) via inductive coupling has a wide variety of applications, such as implantable medical devices (IMDs) that substitute sensory or motor modalities lost to an injury or a disease, or collect information from the nervous system and send outside of the body for further processing. Among popular examples of this group of IMDs are the cochlear implants, visual prostheses, and invasive brain-computer interfaces (iBCI). The use of WPT is expected to see an explosive growth over the next decade as engineers try to cut the last cord for recharging the batteries of mobile electronics, small home appliances, and electric vehicles. In this talk, two novel techniques will be presented for efficient and adaptive inductive power transmission and management. The first technique, called Q-modulation, is an adaptive scheme that offers on-the-fly load matching against a wide range of loading (RL) and coupling distance variations in inductive links to maintain optimal power transmission efficiency (PTE) at all times. It is particularly suitable for applications where the loading and position of the coils can vary, rendering the predefined impedance matching circuits suboptimal. In Q-modulation, the zero-crossings of the induced current in the receiver (Rx) LC-tank are detected and a low-loss switch chops the Rx LC-tank for part of the power carrier cycle to form a high-Q LC-tank and store the maximum energy, which is then transferred to RL by opening the switch. By adjusting the switching duty cycle, the loaded-Q of the Rx LC-tank can be dynamically modulated to compensate for variations in RL. The second technique, called automatic resonance tuning (ART), can compensate for any capacitive parasitic of the Rx LC-tank introduced by the tissue in IMDs or the presence of a conductive object in charging applications. In ART, an array of switched capacitors are locally swept across the Rx LC-tank until the maximum voltage is achieved. This ensures that the LC-tank is tuned to the power carrier frequency. A combination of Q-modulation and ART ensures that the Rx LC-tank is tuned at the optimal frequency and loaded with the optimal RL during operation.

In this talk I will provide an overview of various technologies that are currently under development for wirelessly powering scientific instruments implanted or attached to small freely behaving animal subjects to collect a variety of electrophysiology parameter, apply stimuli, or deliver drugs for scientific research, medical device evaluation and testing of new medications. In many of these experiments, particularly those that are related to the animal behavior, it is important to create an enriched environment for the animal subjects in order to minimize bias. Therefore, eliminating tethers or bulky battery-powered devices that may otherwise be needed would be necessary.

Wireless power transfer (WPT) is one of the most promising technologies with huge market impacts, and the commercialization progress of the mobile devices and electric vehicles using WPT technology are being accelerated. However, when more and more WPT systems are developed, the concerns on the electromagnetic interference to other electronic devices or human bodies are consequently increasing, because the WPT system is designed to transfer high power rather than small communication signal. Therefore, the interests on the electromagnetic compatibility (EMC) issues for WPT systems are also increasing in standardization and product development. In this talk, the EMC issues for the magnetic resonant WPT system in kHz and MHz range is discussed. Although the researches on the EMC solutions for general electronic systems have been done for decades, more effective methods are necessary for this low-frequency high-power system applications. The recent advances in electromagnetic field reduction are introduced. The magnetic field shaping, active/passive/reactive shielding, and filtering techniques are investigated, as well as traditional electromagnetic interference reduction methods, for wireless charging of mobile devices.

This presentation demonstrates the high efficient rectenna topologis with high impedance antennas and their implementations in 500MHz and 2.4GHz bands. The 2.4GHz band recttenna is consisting of the bridge type rectifier that realizes full-wave-rectification without large sized filters.By employing the topology, further downsizing and integration can be achieved easily. High impedance operation with the folded dipole antenna with a 470O is employed to improve the rectification efficiency. 80% efficiency can be achieved. This value is the top-level performance with the commercial-based Si-SBD. Also the size of the 2.4GHz band rectifier is 4.5mm × 4.8mm that is the smallest implementation than the past works. he 500MHz band low power rectenna is consisting of the Cockcroft-Walton type rectifier that can achieve the high output DC voltage with the low input power. To improve the rectification efficiency, the folded dipole antenna with a 1.6kO impedance is employed for achieving the high RF voltage fed to the rectifier. The developed rectenna achieves the output DC voltage of 0.41V and the rectification efficiency of 43.1% at -14.9dBm.

The vision of realizing the Internet of Things (IoT) pervasively connecting large number of sensors and devices requires development of novel solutions for supplying the energy required for the operation of these devices. RF energy harvesting is considered as a cost-effective solution for powering up low-power wireless sensors eliminating the need of on-board batteries. The major challenge of scavenging RF energy is the limited signal strength of the RF waves and the low efficiency of the harvesting circuit at low input power further limiting the amount of energy harvested. While many device and circuit techniques have been suggested to improve the efficiency of RF-to-DC power converters, the fundamental trade-off between low threshold voltage and high leakage current prevents these converters to achieve high power conversion efficiency. To further improve the efficiency of these converters, we propose an adaptive threshold-compensated RF-DC power converter that uses minimal additional circuitry to increase the threshold-voltage compensation of forward-biased transistors and decreases the compensation voltage of reverse-biased transistor thereby adaptively increasing the forward-current and reducing the reverse leakage current.

Closed-form equations have been developed that calculate the maximum output power and energy-conversion efficiency for an energy-harvesting circuit under power-optimized waveform excitation. The theoretical model predicts how signals with high peak-to-average power ratios increase the output power available at low input powers and decrease the maximum energy-conversion efficiency at high input powers. The model shows agreement to within 0.7 dB with ideal simulated components. Additionally, the model provides a theoretical bound for a realized microwave energy-harvesting circuit prototyped at 5.8 GHz.

This presentation reviews and summarizes the state-of-the-art development in the wireless power harvesting at millimeter-wave frequencies. To begin with, CMOS techniques are shown in the design and development of self-powered active tags at 35 GHz and beyond for integrated millimeter-wave identification (MMID), tracking and positioning applications. A number of innovative architectures and circuit examples are discussed with simulated and measured results. Then, millimeter-wave harvesting techniques are further presented through the use of various diode techniques with the demonstration of practical examples up to 94 GHz. Future R&D; directions for millimeter-wave power harvesting are pointed out.

This walk will highlight design challenges in powering small chip scale devices with wireless power transfer. Two application drivers will be presented, including a wireless-powered pad-less single-chip radio is implemented in 65 nm CMOS for applications in Internet of Things (IoT) and wireless tagging of integrated circuit packages. This first example is a fully-self-sufficient mm-wave radio has no pads or external components (e.g., power supply), and the entire radio is a single chip with dimensions of 3.7 mm by 1.2 mm. To provide multi-access, and to mitigate interference, it uses two separate mm-wave bands for RX/TX and integrates both antennas to provide a measured communication range of 50 cm. The transmitter uses a modified Multipulse Pulse Position Modulation (MPPM) with 2 GHz of bandwidth on a 60 GHz carrier to communicate the data sequence as well as the local timing reference. The entire system operates with standby harvested power below 1.5 µW and achieves an aggregate data rate > 12 Mbps. The second example will highlight inductive power transfer to an extremely small 100µm by 100µm tag implemented in CMOS technology. Such a tag is small enough that it can be embedded into the package of other integrated circuits. Power transfer and communication using mm-waves in the near-field will be discussed to deliver 100µW of active power to the tag.

Typical frequency synthesizers based on phase-locked loops suffer from a tight trade-off between integrated phase noise and power dissipation. This compromise poses a severe limitation to the realization of ultra-low-power local oscillators for Internet-of-Things applications. To break this trade-off, several recent works leverage sub-harmonic injection locking to widen the phase-noise filtering bandwidth of a phase-locked loop, and reach lower phase noise at same power. In this talk, the two main architectures implementing this concept, such as the injection-locking-based phase-locked loop and the multiplying delay-locked loop, will be reviewed. A novel theoretical model based on the phase-domain response will allow us to compute phase noise and lock range of such circuits. Then, we will move to discuss the most recent advances in the design of CMOS multiplying delay-locked loops, and show how to achieve fractional-N resolution, and how to automatically calibrate the phase-detector offset that is source of large reference spurs.

The harmonic oscillator is a truly fundamental block in any radio, and its performance in terms of phase noise and frequency range often determines the quality of the whole radio transmit-ter/receiver. The goal of this talk is to clarify the phase-noise and tuning-range capabilities of a harmonic oscilla¬tor integrated in a silicon (and particularly CMOS) technology. We will start by reviewing a rigorous, yet intuitive, time-variant theory of phase noise and its application to the most popular harmonic oscillator topologies, capturing the complex behavior of noise conversion into phase noise, primarily with respect to the impact of thermal noise sources. Thereafter, we will examine various approaches to achieve a very wide frequency tuning range, preferably in excess of one octave, focusing on CMOS designs. Abundant examples from the state-of-the-art will support the theoretical analysis.

IoT and CPS are describing a variety of wireless applications, which cannot be served by single radio standard as there are divergent requirements with regard to power consumption, data rate, range, security, robustness etc.. ZigBee, Bluetooth as well as IEEE 802.15.4 in different flavors are used today for short range wireless communication, where new standard serving specific needs like IEEE 802.11.ah and LoRa are emerging. Multi-standard multi-band radios will be required to enable flexible terminals, sensor nodes and gateway, which either can be integrated into networks of the mentioned standards or connect sensors of different standards as a gateway. The talk will review the system requirements of the different standards in order to define a multi-standard multi-band radio architecture suited for SoC integration. Results of multi-standard multi-band transceivers in 130nm CMOS will be presented.

Designing an RF frequency synthesizer that functions well in a larger radio IC or, nowadays, a multi-radio system on a single IC chip, is extremely challenging due to many possible aggressor and victim roles that the synthesizer can unwillingly engage in. In this talk, we examine various coupling paths through which an RF oscillator, being the most sensitive circuitry in the entire radio, can be disturbed. We then investigate possible system-level solutions, chiefly via frequency planning, such as fractional frequency division, that can put the oscillator out of reach to the aggressor’s harmonics. For systems unable to exploit the fractional dividers, we also offer time-domain solutions in which the aggressor phase would be aligned to minimize the interference. Finally, we offer circuit-level solution to minimize the oscillators sensitivity.

The VCO unwanted pulling has been historically a major issue in wireless systems and particularly in direct-conversion transmitters. Despite versatility, direct conversion transmitters suffer from the local oscillator disturbance by the PA through unwanted couplings. This often leads to a drastic degradation of EVM and emission mask. To alleviate this, time-consuming and often unpredictable optimization of floor plan, package, and PCB is required to maximize the isolation between the PA and the VCO. Moreover, in many modern radios it is common to have more than one VCO on chip to support various features such as FDD, carrier aggregation, or coexistence, further exacerbating the problem through multiple VCOs cross-coupling. To address these concerns a new calibration scheme is proposed that corrects any pulling effect regardless of its source or magnitude. The proposed calibration deals with the pulling issue through system level, rather than minimizing sources of pulling as is commonly done.

In 2015, there were 5 billion connected IoT devices, and this number will soon exceed the number of cellular handsets in use. The design targets posed by low power IoT standards with duty-cycled operation such as Bluetooth Low Energy and 802.15.4 are different from those posed by the cellular or WiFi market, requiring an intense focus on low peak and average power, fast start-up time, and minimum form factor. This talk will describe several solutions to the oscillator design challenges that have helped to enable today’s low power, small size, and low cost wireless sensors nodes including accurate yet low power synchronization clocks, fast startup for the RF synthesizer reference oscillator, and low power RF VCOs. At the end, attendees will have a solid overview of the oscillator circuit innovation needed to help drive the market growth to 25+ billion connected devices that is predicted within the next five years.

A phase-locked loop (PLL) based frequency synthesizer is adopted in various systems. In a PLL design, other than demanding good signal purity (i.e. low phase noise and low spurs), locking speed is also an important requirement. In circuits for IoT, energy consumption is a primary design consideration. By shorting the lock time, a fast-locking PLL reduces energy waste by minimizing the energy consumption during the settling process, which is a desired attribute for an IoT system. A PLL requires a certain amount of time for the loop to settle and acquire phase/frequency lock. This settling time is determined by the loop characteristics and is inversely proportional to the loop bandwidth. To shorten the locking time of a PLL, the most straightforward solution is to widen its loop bandwidth. However, some aspects of noise and reference spur performance are comprised. In this talk, several techniques to shorten the locking times will be presented.

Active implantable medical devices utilize systems of activating and sensing components to reverse the effects of disease and disability. Until recently, these systems typically involved a single primary implanted enclosure that incorporated all of the processing and sensor capabilities. However, it is frequently necessary to sense and control disparate regions of the body, necessitating novel concepts in the architecture of implantable systems. One system being developed, the Networked Neuroprosthetic (NNP) System, consists of a network of implantable modules that can be distributed throughout the body. The NNP System is capable of meeting the technical requirements of a wide variety of clinical applications involving activation, sensing, and closed-loop control. The first application of the NNP System is as a neuroprosthetic system providing electrical activation of paralyzed muscles in individuals with spinal cord injury. Future targeted applications include systems for control of motor function in stroke and systems to alleviate chronic pain. The modular implantable concept provides a platform upon which clinical applications can be developed for a multitude of neurological disorders.

This talk will present the development of an ultrasound pill camera for imaging the digestive track. Simulation of b-mode imaging of the small intestine showed that a rotating sub-array of 16 elements in a 128 elements array, operating at 5 MHz, wrapped around a 1 cm pill, and with a fixed focus on transmit and receive with an F-number = 4, provides images with good diagnostic value. First, we will describe the design, fabrication, and integration of a flexible 128 elements capacitive micromachined ultrasound transducer (CMUT) array on a flexible printed circuit board. Next, we will describe the development of an application specific integrated circuit (ASIC) and a wireless transmitter, responsible for the ultrasound imaging functions (beam forming on transmit and receive, time gain control, and analog to digital conversion) and beam formed image transmission. The predicted lifetime of the pill cam is eight hours at a frame rate of 4 b-mode images per second.

Retinal degenerative diseases lead to blindness due to loss of the “image capturing” photoreceptors, while neurons in the “image-processing” inner retinal layers are relatively well preserved. Information can be reintroduced into the visual system using electrical stimulation of the surviving inner retinal neurons. Some electronic retinal prosthetic systems have been already tested in human patients and approved for clinical use, but they are limited by very low resolution and very difficult implantation procedures. We developed a photovoltaic subretinal prosthesis which converts light into pulsed electric current, stimulating the nearby inner retinal neurons. Visual information is projected onto the retina by video goggles using pulsed near-infrared (~900nm) light. This design avoids the use of bulky electronics and wiring, thereby greatly reducing the surgical complexity. Optical activation of the photovoltaic pixels allows scaling the implants to thousands of electrodes, and multiple modules can be tiled under the retina to expand the visual field. We found that similarly to normal vision, retinal response to prosthetic stimulation exhibits flicker fusion at high frequencies (>20 Hz), adaptation to static images, and non-linear summation of subunits in the receptive fields. Photovoltaic arrays with 70µm pixels restored visual acuity up to a single pixel width, which is only two times lower than natural acuity in these animals. If these results translate to human retina, such implants could restore visual acuity up to 20/250. With eye scanning and perceptual learning, human patients might even cross the 20/200 threshold of legal blindness. Ease of implantation and tiling of these wireless modules to cover a large visual field, combined with high resolution opens the door to highly functional restoration of sight.

We have developed a novel wearable device, the Brain Stethoscope, for fast and accurate detection of brain rhythms by turning brain electrical activity into sound. The Brain Stethoscope is a self-contained, affordable, point-of-care device for detection of abnormal brain waves within seconds especially for those with no clinical signs. The device transforms EEG (electroencephalography; brain waves) signal in real-time to easily interpretable sounds. It consists of scalp electrodes, connected to a small circuit board containing an analog amplifier, analog-to-digital converter, a wireless transmitter, and a rechargeable battery. The digitized EEG signal is transmitted and stored in an encrypted format. The raw and unfiltered signal can then be transformed into a synthetic voice using a patented sonification algorithm. The device requires minimal training for set up and interpretation, and can be used by both healthcare professionals and non-expert caretakers. Our research has validated that sonified brain signals can be used to detect seizures with very high sensitivity and specificity (~90%). The Brain Stethoscope offers the advantages of simple, fast, easy, and real-time detection of seizures as an alternative to time consuming, labor intensive, and expensive conventional EEG recording. The Brain Stethoscope will help patients, caregivers, and health care providers improve epilepsy care while potentially saving millions of dollars in health care costs. The device can be used in any setting including hospitals, clinics, home, and is especially attractive to those with limited resources.

Electronic devices for implants face specific challenges related to the biomedical context. We present state-of-the art and advanced IC architectures addressing these challenges for biosignal recording, processing and control: low S/N and low-frequency signals, multiple sources, safety, adaptability, signature identification, electrodes matching, data compression, data transmission. Key issues related to neural and cardiac implants are presented. Recent advance on the electronic artificial pancreas are presente

Today’s commercial implantable medical devices (IMDs) such as the pacemaker, deep brain neurostimulators and peripheral nerve stimulators are bulky and invasive due to the use of batteries and wired interfaces. Wireless powering and extensive miniaturization of these implants is crucial for making them minimally invasive and eliminating discomfort and the risk of infection for patients. Providing high power levels to miniature implants located deep inside the body is a big technological challenge. In addition, a robust, bi-directional data communication link with the IMD is essential for most applications. Conventional techniques for wireless power transfer, such as inductive coupling and RF far-field power transfer, are inadequate for transferring high power levels to miniature, deep-tissue implants. We use ultrasound for power transfer since it has wavelengths comparable to the size of the implant, which enables focusing of the energy at the implant, leading to a higher link efficiency and lower heating in surrounding tissue as compared to RF powering techniques. It is also feasible to design piezoelectric receivers with a favorable impedance profile, to allow for more efficient power recovery, as compared to electrically small antennas. In this talk we will describe the design of a platform implant technology based on ultrasonic power delivery. An overview of recently designed systems together with measurement results will also be provided.

Ultrasonics has been used in a number of biomedical and civil application ranging from medical ultrasound devices to beam deformation non-destructive testing. Ultrasonic pressure waves have been used naturally for thousands of years by animals for navigation and communication, with the prime examples being bats with ultrasonic navigation through air and dolphins with ultrasonic communication and navigation in water. This talk investigates on signal propagation within the human being by means of intra-body communications without radiofrequency waves but, instead, with lower (if not deeply lower) frequency waves. An exhaustive review of up-to-date propagation modes in water-like vectors is performed and experimental measurements allow the setting up of a comparison with conventional propagation. A practical demonstrator has been developed to characterize within a low frequency range the ultrasonic wave propagation.

An upcoming short range communication technology for body area networks is intrabody communications. In this technology a signal is either galvanically or capacitively coupled through the body to send data. This necessitates the signal to either use the human body as an electrical conductor (low frequencies) or as a support surface for surface plane wave propagation (higher frequencies). By studying the effects of electrical properties of tissue on signal propagation, we have proposed additional applications of signal coupling through the human body. Some of the applications to be explored include monitoring real time human body hydration, implant communications and using the human body as an antenna. We will present some modeling and empirical results from our current work as proof of concept.

Standard health monitoring devices have the potential to capture movement, activity and electrophysiological data from patients in the home setting. However, these devices contain conventional electronics, which consist of bulky and packaged components, which typically do not bend, stretch or conform to the curvilinear shapes of the human body. These limitations pose a serious challenge for patients with cardiac or movement disorders, which require continuous tracking of health symptoms to monitor compliance or efficacy of drug regimens. Devices that achieve intimate mechanical coupling with the body may thus help to prevent medical problems in high-risk neurological and cardiac diseases. Here we describe new mechanical and electrical design strategies for wearable and implantable medical devices with physical properties that approach that of soft biological tissue. These ‘epidermal electronics’ have enabled emerging stretchable wearable systems that can monitor motion, physiology and electrophysiological activity in the hospital and home settings. The sensors (i.e. electrodes, temperature sensors, gyroscope and accelerometers) and associated circuitry (i.e. microcontroller, memory, voltage regulators, rechargeable battery, wireless communication modules) and spring-like interconnects are all contained as embedded components within an ultrathin, stretchable elastomeric substrate. Quantitative analyses of systems mechanics during cyclical exposure to stress illustrates the ability of the epidermal electronics to mechanically couple with soft tissues, in a way that is mechanically invisible to the user. These results highlight the soft and stretchable form factor achieved and multimodal sensing, which is ideally suited for monitoring physiological signals from different regions of the body in patients.

5G plans to provide multi-Gigabit data rates enabling, for example, two way 4K streaming video. With this high speed data requirement it is clear that bands with hundreds of megahertz of bandwidth will be required. That is what drives the frequency of operation into the mmWave bands. These added bands at high frequencies will have a dramatic impact on the mobile phone front end block diagram and the technology required to implement them. This presentation will overview the front end module architecture and the fundamental technologies required to achieve these new 5G designs.

With ft and fmax above 300 GHz, flexible metallization approaches and high integration levels, scaled CMOS technologies are poised to provide high performance and broad functionality for cm- and mm-wave 5G applications. To increase voltage handling and output power, FET stacking is becoming widely practiced, particularly using SOI technologies. This paper reviews recent single chip MOS PA results, including >250mW and peak PAE up to 29% at 28 GHz without power combining; 640mW at 45GHz, and 240mW at 94GHz using spatial power combining. Broadband modulation and predistortion results are presented. Directions needed for future development to meet prospective 5G requirements are also highlighted, including issues of high backoff efficiency and linearity.

In recent years, the topic of 5G has led to wide open brainstorming. To start with, an overview of the current trends emerging 5G radios will be presented. These trends are pointing towards very real, concrete, challenging power amplifier and RF front-end design issues. Some features are more near term and others are further out. There are low power applications for the Internet of Things, and wide bandwidth, high throughput connected applications. The luxury of having 5x the bandwidth will be lost with wide modulation bandwidths, making many of the simplified handset DPD techniques less practical. These challenges, and others, will be explored in this presentation.

This session will cover topics of the design of millimeter-wave MMIC power amplifiers (PA) for the application of 5G communications. The design methodology and techniques to develop highly-efficient MMIC PAs will be discussed. There are multiple options for process technologies, GaAs HEMT and GaN HEMT for the design of mmW MMIC PA. This presentation will discuss the trade-offs between the cost and the performance of different device technologies and design topologies. I will discuss design and results of millimeter-wave power amplifiers that Qorvo has developed up to the date. The main frequency band of discussed PAs is 28-31 GHz (Ka-band) and the level of output power covers from 25 dBm (316 mW) to 37 dBm (5W). For commercial markets of mmW MMIC PAs, the compact design of the power amplifiers becomes a critical factor due to the cost of MMIC PAs. The challenges for the compact design of mmW MMIC PAs will be discussed in conjuncture with significance of EM-simulations in the design. The advantage of a GaN PA in commercial millimeter-wave market, especially for base station, is discussed by comparing it to similar GaAs power amplifiers. This presentation will examine the blueprint of insertion of millimeter-wave MMIC power amplifiers into 5G applications.

The 5G system may need power amplifier operation at mm-wave band around 28GHz. To get a high performance at the high frequency, the power gain of a transistor should be high, requiring a small gate transistor. It can be pursued using compound semiconductor devices but the open foundry services do not provide an adequate device for the amplifier. Rather, CMOS transistor with a small gate is better suited for the amplifier. Therefore, we have pursued a CMOS linear power amplifier using 28 nm processes. The cascode linear PA with 2.2 V operation provides a power gain of 13dB. For the LTE signal with 7.5 dB PAPR, this amplifier delivers 15.3dBm linear output power with 28.4% PAE and -30dBc ACLRE-UTRA . It is expected that the performance will be further improved by Doherty amplifier operation based on the CMOS PA. The detailed design procedure will be described.

Over the past few years, there has been an explosion in the mobile data usage mostly due to the increasing number of tablets and smart phones in use. To support such demand, wider transmission bandwidths are needed, and hence, the technique of carrier aggregation (CA) has been introduced in 4G cellular systems. This enables scalable bandwidth expansion beyond the single LTE carrier by aggregating two or more LTE component carriers of similar or different baseband bandwidth, which can be chosen from the same 3GPP frequency band (intra-band) or different 3GPP frequency bands (inter-band). Furthermore, CA is supported by both FDD and TDD modes, and this offers the optimum flexibility in the way the spectrum is utilized and how the network scheduling is configured. This talk will discuss the resulting increased systems complexity due to CA in the radio RF front-end and transceiver architecture, and address key CA related RF design challenges.

Carrier aggregation poses significant challenges for LO generation circuits. Due to the proliferation of bands worldwide for LTE, the LO generation circuit is called on to support generation of multiple frequencies with nearly arbitrary relationships to each other. Due to the inherent non-linear properties of LO generation circuitry, many higher order spurious products are generated. Special care in the system design is required to ensure that these spurious responses within the LO chain do not produce unacceptable spurious in either transmit or receive circuitry. Coupling mechanisms between the multiple frequency generation blocks need to be minimized with careful layout and supply regulation. Use of adaptive IF frequencies in the receiver can significantly improve the spurious response issues.

This presentation describes an LNA and mixer receiver front-end architecture for LTE-A which can support multiple modes and multiple aggregated carriers. Several techniques to implement an intra-band and inter-band carrier aggregation (CA) receiver front-end will be reviewed. The case of non co-located intra-band on circuit implementation is also discussed as well as the impact of the different CA implementations on noise figure and power. A concept called hybrid-CA is proposed for better noise figure when implementing 2 and 3-CA. A new advanced node CMOS compact low-noise amplifier (LNA) that addresses the increasing number of LNAs for multi-band and several carrier aggregation combinations is analyzed. Moreover, the impact of LTE-U bands on receiver design for extended carrier aggregation is addressed.

With limited availability of contiguous spectrum and the demand for higher bandwidth, the phone Carriers are moving to carrier aggregation of 2 or 3 bands to fully use the available spectrum. The carriers could be in the same band (Non-Contiguous CA) or up to 3 different bands (Inter-band CA). To keep the platform cost down and simplify radio board design, it is desirable to minimize the extra front end components and move to single ended RF ports. This is complicating RFIC design; different coupling mechanisms from PA, TX port outputs and between VCOs limits the achievable sensitivity of the receiver. In this talk we discuss different design trade-offs and architecture choices to support Carrier Aggregation of up to 3 bands.

Recently, there has been great research activity directed towards developing next-generation and 5G wireless systems which aim to deliver speeds and capacities which are order of magnitudes higher than what is available today. Some of the key enabling technologies in 5G are Massive MIMO, carrier-aggregated communications, concurrent multi-band transmission along with the use of the mmWave spectrum. While these are attractive technologies, they bring many challenges in terms of the RF front ends used. Therefore, one of the major bottlenecks along the path towards to realizing green and sustainable 5G networks is the RF front ends and the many challenges they bring, such as nonlinearity, distortions, energy efficiency and compactness. In this presentation, the design and linearization of concurrent, carrier-aggregated, multi-band and MIMO transmitters is discussed, with an emphasis on linearization techniques and state-of-the-art digital pre-distortion techniques.

Conventional Inter-band carrier aggregation receivers use either multiple antennas or filter banks to split carriers from different frequency bands. Demands on the aggregation of more frequency bands and the large number of band combinations challenge the design of global roaming device. We present a frequency-agile, scalable concurrent receiver array that supports highly flexible inter-band carrier aggregation combinations. Frequency-translating quadrature hybrid (FTQH) techniques are used to realize massive independent concurrent receivers that share a single wideband antenna and present a wideband matched input impedance. Multiple chips can be further connected with a low loss RF daisy chain to increase the maximum number of supported carriers as needed. Each receiver has independently programmable gain, bandwidth, NF and power consumption depending on the RF environments and application context.

The thirst for superior SOC performance and cost has advanced the use of nanoscale CMOS technologies to solution complex analog-intensive designs. This workshop with describe several mainstream advances in CMOS, with focus on understanding performance tradeoffs, design techniques, design challenges, and the associated manufacturing complexity of these modern process solutions. Emphasis will be placed on three CMOS process derivatives including Planar High K Metal Gate, Fully Depleted SOI, and FinFet CMOS technologies at geometries at 28nm and below. Performance assessments will be shown across several design disciplines including digital block Power-Performance-Area, analog-design figures of merits, and end-to-end design reference flow complexity.

Continuous scale down of CMOS technology makes several known issues in RF/analog circuit design further challenging. Large magnitude of local/random fluctuation as nature of small dimensions, strong influence from parasitic components to effective device performance, and significant layout dependent effects are well known examples. Further, recent drastic changes in MOSFET structure such as HKMG and multi-gate architecture (FinFET, FDSOI) induces new issues such as limitation of high frequency operation due to (ironically) large gate resistance and channel temp increase caused by self-heating. In addition, low supply voltage along with aging effects makes design sign-off window very narrow. Capturing these effects and limitations in design kits and environment is new exciting challenge for high performance, low power, and highly reliable RF/analog circuit design. In this talk we’ll review those issues from a viewpoint of process/device technology and discuss solutions with paying special attention to RF/analog design.

Digital RF architectures are best suited to benefit from the technology improvements of deep submicron technologies as 28nm and beyond. We will present measurements and simulation results of RF circuits in 14nm and 28nm technologies to demonstrate how the power consumption can be further reduced by future technology nodes. The circuits include RF receivers, RF transmitters, mixed signal blocks and synthesizers. The target applications are cellular standards as 3G (UMTS) and 4G (LTE). One key enabler for the significantly lower power consumption in 14nm is the lower supply voltage. The other measure is to increase the clock frequency of the mixed signal blocks to RF-like frequencies. Consequently, more analog complexity is transferred to more complex digital signal paths which benefit most from the advanced digital process technologies.

The high-performance, low-power demand on application processors (APs) in mobile devices keeps driving the SoC providers to follow closely with the most advanced technology. While analog interface is still considered efficient for data communication between the RF and AP dies, ADC and DAC designs in advanced processes are inevitable. This talk will evaluate the technologies beyond 28nm from the mixed-signal circuit designers’ point of view. Several design examples will be provided to demonstrate the design strategies for taking the advantages in advanced processes as well as reducing the effort during process migration. The increasing requirements on the simulation and layout resources will also be addressed. This talk will be concluded with a glance of the upcoming challenges in 10nm FinFET process.

In this talk, we focus on the key challenges and solutions in verification of analog/RF/mixed-signal integrated circuits in advanced nanometer CMOS nodes – focusing on both the increasing circuit complexity as well as the increasing number of dimensions of verification. As designers push the limits of circuit techniques and process technologies, previous third- and second-order physical effects begin to appear as first-order effects which have a dramatic impact on the electrical performance – and thus design margins and yield. Included here are the effects of such items as device noise, parasitics, layout-dependent effects, electro-migration, variability and mis-match. In order to achieve competitive designs, it becomes critical to understand these effects properly and how they impact circuit performance. Moreover, new targets for these custom circuits, especially along the energy consumption patterns, bring new requirements and increase the risk of working first-silicon around the various types of active and standby power consumption. The increasing use of digital-techniques brings another dimension rapidly growing in complexity. Finally, objective-driven simulation strategies are required to accurately characterize circuits at many nodes, and statistical analysis and verification techniques become a key requirement in order to quantify the required design margins. We will review the key recent advances in verification technology and their successful application across a variety of analog/RF/mixed-signal projects in both planar and bulk advanced nodes - demonstrating how they can help to ensure first-silicon success.

The use of millimetre wave frequencies for high data rate communication seems to be the answer to the increasing spectrum demand. Many different applications are demanding to take to the next level the millimetre wave electronics: for example, 5G is no more just a trendy term, the telecom industry is investing heavily on it; at the same time, WiGig is considered as the tomorrow’s WiFi. This brief introductory talk will list the main applications, not limited to the communication market, where the major investments in the millimetre wave electronic industry are expected. Then, it will describe the main open issues that the researcher community is asked to focus on in the next years, in terms of technology, circuit and system solutions.

As the demand for higher data rates pushes wireless technologies to their limit, unprecedented challenges meet every aspect of modern transceivers design. In the backhauling market, these range from RF MMIC technological improvements to digital modem revisions and even up to architecture-level upgrades: MIMO, Frequency Reuse, Full Duplex are instances of such hot themes. A glance to current techniques and perspectives is discussed for the 5G world while focusing on potential outcome and requirements.

Microwave Digital Radio Link systems have been continuously challenged by though product requirements like improving spectrum efficiency, increasing capacity and reducing the total cost of ownership. This continuous evolution in the market scenario has demanded through the past years a tremendous development of the transceiver technology, making possible the achievement of extremely high levels of reduction in power consumption, cost and form factor while improving electrical performance, yield, reliability at an increasing operating frequency. These trends will be described with a good level of details showing how additional emerging technologies can offer an effective way to further increase the achievable performance.

Today, almost all radio manufacturers have E-band (70/80 GHz) radios in their product portfolio and the competition of offering a radio with higher throughput; longer radio hops and to the better price is important to attract mobile operators. For the transmitter in such radio equipment, the most critical component is the power amplifier. Parameters such as output power and linearity are the two most important parameters for being able to use high modulation formats and output power for long distance communications. Digital pre-distortion techniques are nowadays common practice to linearize amplifiers. Usually for microwave radios, this technique is implemented in the digital domain at the expense of increased bandwidth in the digital/analog converter (DAC). At mm-wave frequencies, when the signal channel bandwidth is much wider, the increased signal bandwidth used in the DAC will consume considerably higher power, making this technique inappropriate to use for enhancing the radio performance. Analog pre-distortion of power amplifiers on the other hand can be implemented at mm-wave frequencies with little or no added power consumption to enhance the linearity. We present the design, performance and challenges of a linearized PA at E-band.

MM-wave antennas are compact, with high gain and normally very high directivity. Increasing requency the mechanical manufacturing becomes critical, due to the small wavelenght. For specific applications ad-hoc solutions should be proposed, as shown in the present talk for Eyewear Devices

It has been nearly 5 years since millimeter wave radio chips first exited the reseach lab environment to the world ready and looking for industrial market applications. Now considered as commercial products, these integrated circuits have not achieved yet the production momentum and cost downs seen in the Wifi driven sub 6 GHz chipset market. To illustrate, RFCMOS integration was instrumental in decreasing overall sub 6 Ghz chipset BOM costs, thus greatly contributing to the penetration of wireless modems into consumer mass markets. For millimeter wave radios, silicon integration alone may not be sufficient to overcome the cost barriers to mass market adoption. Indeed costs, quality requirements, infrastructure limitations, and equipment maturity are major inhibitors to the scaling of the millimeter wave radio chipset supply chain. This keynote will highlight the significant constraints, their impact and pitfalls they create, while presenting potential solutions that can be considered.

The interaction mm-wave human body is an hot topic both at research level and from the population. Positive interactions (diagnostic, cancer discovery and elimination) or negative (it is dangerous for humans) arises daily. The presnt talk tries to clear a little the fog, giving some scientific evidences of the true interaction waves, humans.

The talk will first examine some systems where pulsed kW-level RF transistors are needed. The implications of the required pulse length, duty cycle and pulse shape on the linearity and thermal properties of the transistor will be discussed, and the necessity for gate or drain bias pulsing will be demonstrated. A technology comparison of Si bipolar, LDMOS and GaN transistors will be given and it will be shown that there is no clear winner. Finally, the state of the art in very high voltage GaN transistors that operate from a 150V drain supply voltage with 20W/mm power density will be given and their potential for multi-kW devices described.

Over the past decade, LDMOS (laterally-diffused MOS) microwave power transistor technology has experienced remarkable gains in frequency range, power, and efficiency while simultaneously reducing cost. These advances, which result from the high-volume manufacturing and continuous improvement of LDMOS technology driven by base station requirements, have expanded the practical application of solid-state microwave technology into applications currently dominated by magnetrons. We discuss the architecture of SSPAs (solid-state power amplifiers) for 915MHz and 2.45MHz magnetron applications, and present the architecture and performance of 2kW, 915MHz and 1kW, 2.45GHz reference designs.

Many advanced applications, like Radar, EW and EMC require ever greater power over a broadband and within a compact size, yet with high repeatability, reliability and long life for a high load mismatch. These requirements impose many challenges including thermal instability and high inter-circuit electromagnetic (EM) coupling, significantly influencing the performance of a high power GaN PA and system. This presentation will cover design and integration difficulties, and the advanced techniques for realizing GaN HEMT PAs with very high CW (P1dB) power (kW) over an ultra-wide bandwidth (multi-Octave to a decade). This will highlight the novel design methods to overcome inherent shortcomings of GaN devices, like memory-effect, soft compression, etc. Further, advanced integration/assembling technique for overcoming EM coupling, RF leakage, achieving a long life with high reflection, 100%, high modulation recovery, etc. will be discussed. Finally, the test results for the advanced GaN PAs delivering CW (P1dB) power > 1 kW over more than a decade bandwidth will be presented.

In this presentation, a three-way inverted Doherty power amplifier (DPA) using Infineon’s latest LDMOS (LD11) technology and T3PAC package is introduced. The LD11 provides great performance enhancement, and T3PAC has advantages of high performance and low cost. The combination of LD11, T3PAC and three-way inverted DPA provides a high performance, low cost and wide-band solution for the high power / high efficiency base-station applications. A three-way DPA is fabricated and measured. In the working frequency bands, 2.11 to 2.2 GHz, the proposed three-way DPA provides 51.2% to 52.2% drain efficiency (DE) at 8 dB power back-off, 53.3% to 54.1% DE at P3, 15.3 to 15.7 dB gain, and 58.7 dBm to 58.8 dBm P3.

The linearity of power amplifiers is becoming highly important because of the use of spectrally efficient modulations for communications application, the desire to use single big amplifiers for multifunctional applications, and the utilization of complex waveforms in radar and related purposes. This presentation will discuss techniques for the cancellation of distortion that are known as linearization and their use with very high power solid-state amplifiers. Linearization is even more effective for very high power applications because amplifier nonlinearity often increases with device/amplifier size, and the economic trades in applying linearization increase with amplify size. Different methods of linearization including digital approaches will be introduced and compared, and results presented for the linearization of very high power microwave amplifiers.

Recent substantial advances in GaN products and technology coupled with low loss multi-element combining techniques now enable effective kilowatt level solid state amplifier alternatives to traveling wave tube amplifiers (TWTAs). This workshop presentation examines some of the trade spaces in which designers must operate and offers some practical limitations on achievable power levels as they apply to different combining techniques. CW versus pulsed operation, thermal management options, performance versus bandwidth and frequency, and advantages of various combiner structures are examined.

Automotive radar and thus ADAS based on radar has been in development over decades – in1998 Mercedes-Benz went into series production for premium cars, becoming worldwide since then, in 2012 the ADAS democratization process, i.e. the employment in smaller – lower budget cars – has begun as well at Mercedes-Benz with the then - new - 2012 B-class. Until mid 2015 Infineon had sold 10 million 77 GHz chipsets worldwide, Valeo and Hella have sold each more than 2 million 24 GHz BSD (Blind Spot Detection) units in 2015. New cars out of today’s production are equipped with a lot of different ADAS units - based on radar, lidar or cameras. In 2012 the “Drive Me” project in Sweden was started by Volvo Cars to put 100 autonomously driven vehicles on the urban roads of Gothenburg until 2017, being endorsed by the Swedish Government and based on the available SARTRE results. The aim is to pinpoint the societal benefits of autonomous driving and position Sweden and Volvo Cars as leaders in the development of future mobility. The scope to start with: 70 km/h max. – no on-coming traffic – certified roads (maps) will be discussed. In 2015 the Yutong “iBus” - the intelligent urban bus - has shown its unique capabilities on urban streets. On August 29th 26 km were driven entirely autonomously, incl. stops for passenger getting out and in, respecting traffic lights and passing other vehicles on its way …. The environmental conditions: 26 traffic lights passed, vmax: 68km/h, no on-coming traffic (2 lane roads) as well as the employed sensor technology will be discussed. The actual status in this entire field, the pro’s and con’s of the different sensor types, as well as their availability (e.g. weather capability) will be discussed in general. The trends of future development directions towards autonomous driving will be evaluated.

Due to their high flexibility and robustness, self-organizing robot swarms are a promising candidate for use in exploration tasks. In order to completely define the robot swarm local positioning network, 3 translational and 3 rotational degrees of freedom need to be determined for each robot. It will be shown, that the self organization of such a 3D network is an extremely challenging task due to the very high degree of freedom of the network constellation. We will present a solution that uses SIMO FMCW secondary radar units to measure the positions and orientations of the swarm members relative to each other in all dimensions. A depth-first search algorithm is employed for the self-organization of the network. Measurement results with a robot swarm of 5 robots will illustrate the challenges of the measuring task and the capability of the proposed approach.

The United States military maintains satellite communications throughout the world to coordinate military action. As the military communications needs have grown over time, the capabilities of the military satellite communications (MILSATCOM) has grown to meet the needs. Commercial need for spectrum has also increased in the last decade and has encroached upon government spectral needs, including satellite communications. The present MILSATCOM systems and their respective capabilities are summarized with the anticipated capability gaps for future users. Future system concepts are presented that meet future capability needs within the limitation of affordability. One option of meeting these future capability needs is providing satellite communications at higher frequencies such as V-band (71 GHz – 76 GHz) and W-band (81 GHz to 86 GHz). The advantages and disadvantages of satellite communications at these spectral bands are presented along with needed component development.

This presentation will begin with a description of how the Ka-Band device has evolved from the 0.18 um NFP GaN HEMT used below 20 GHz. It continues with a detailed description of a quadrature balanced 12 Watt Ka-Band GaN HEMT MMIC. This MMIC will be compared to a previous generation single-ended PHEMT MMIC highlighting the advantages of GaN. Residual Phase Noise measurements will be presented that are “as good or better than the reference amplifier”. A 4 Watt Ka-Band GaN HEMT MMIC for phased array applications and a 12 Watt 17-40 GHz K/Ka-Band NDPA GaN HEMT MMIC will be described. The final section of this talk will address E-Band device evolution and the designs of 71-76 GHz and 81-86 GHz 1.4 Watt GaN HEMT MMICs.

Gallium Nitride based transistor technology’s characteristics of very high current density combined with high voltage operation have held the promise to improve microwave circuit applications that presently utilize Gallium Arsenide (GaAs) devices. While the advantages of GaN are manifest, many of the features that make GaN transistors attractive can be shown to create significant issues, many of which are not encountered with lower voltage technologies. In this workshop presentation issues, scenarios and strategies applicable to mmW GaN PA MMIC design are discussed, including but not limited to: - Amplifier topology and bandwidth - Network asymmetry and power combining - Amplifier stability and analysis - Thermal considerations - Device modeling and characterization Whenever possible specific examples will be presented highlighting the benefits and problems associated with high frequency GaN MMIC design along with a summary of the current state of the art.

Si CMOS and SiGe HBT technologies have emerged as strong contenders for applications from 300GHz with moderate power levels, low cost, and high levels of integration. Ft and fmax values above 300GHz are readily available from “workhorse” technologies, along with flexible metallization schemes. Peak output powers as high as 560mW at 80GHz and 640mW at 45 GHz have been demonstrated from single chips. 5G mm-wave transmitters for both handsets and base-stations are likely to require peak power in the 0.1-1W regime, generated within ICs that encompass PA as well as LNA, switch and potentially phase shifter. These requirements heavily favor Si.

The last decade has seen rapid advances in the operating frequencies of solid state power amplifiers using Indium Phosphide (InP) High Electronic Mobility Transistors (HEMTs). In particular, power amplification has been demonstrated in packaged MMICs to as high as 850 GHz. This advance has been made possible with a radically scaled 25 nm gatelength transistor with a 1.5 THz maximum frequency of oscillation (fMAX). When combined with scaled frontside and backside processes, a broad range of circuits have been demonstrated, including low noise amplifiers, power amplifiers, mixers and multipliers. This talk will begin with a technology overview describing the transistor, MMIC and packaging approaches. This talk will continue with an overview of recent power benchmarks, and including a discussion on efficiency. Finally, an overview of sub-millimeter wave sources using InP HEMT technology will described.

This talk will review the development of high power solid-state power amplifiers operating between 70-500 GHz using InP HBT. The high fmax of the technology at the 250-nm (700 GHz fmax) and 125-nm (1.1 THz fmax) nodes, combined with breakdown voltages of 3.5-4.5 V allow high-gain, world-class mm-wave and THz PA’s to be realized. After review of the underlying InP HBT technology, the key design trade-offs for PA design in the technology across the cited frequencies will be reviewed – they include which HBT topology to use, choice of wiring environment, DC bias distribution, sources of instability, PA-cell power matching, and RF combining methods. A review of state-of-the-art PA results between 70-500 GHz will be presented. Lastly, examples will be presented to show the prospects and opportunities these high-frequency InP HBT PA’s have in next generation communication, radar, and instrumentation systems.

The last decade has been witness to an explosion in millimeter wave vacuum electronics development. Capitalizing on their inherent strength in wideband power generation, highly efficient TWTs, packaged traveling wave tube amplifiers (TWTAs) and compact microwave power modules (MPMs) have been developed for use in emerging millimeter wave applications from Ka-band to G-band, and everything in-between. This talk will focus on recent achievements in millimeter wave TWT/MPM technology. The performance of other high power millimeter wave vacuum device types will also be reported.

The development of millimeter-wave 1 – 3 W GaN MMIC power amplifiers has enabled the development of high-power solid-state replacements for current and emerging TWT amplifier applications in the 71 to 100 GHz frequency range. The output power levels needed by the new SSPAs can only be achieved by combining significant numbers of this generation of devices. Consequently, high efficiency power combining techniques are required to achieve SSPAs with 50 W or greater power output. This presentation will discuss several E-band and W-band GaN MMIC based 10 W to 50 W SSPAs achieved using high-order planar and radial waveguide power combining approaches.

In recent years there has been major progress in the development of linearizers for millimeter-wave power amplifiers. Linearizers have been produced to 100 GHz and work has begun on extending their upper limit to greater than 250 GHz. Very wideband (>10 GHz) millimeter-wave linearizers have also been demonstrated. This presentation will focus on Ka through W-band linearizer applications. It will discuss the linearization of both SSPAs (GaN and GaAs) and TWTAs (helix and coupled cavity), as well as Klystrons, and provide a road map for what to expect in the future.

Integrated circuits in silicon technologies have already impacted the terahertz field by deploying cost-effective and highly integrated systems for novel applications. The short-wavelength at these frequencies makes it possible to directly integrate terahertz antennas on a chip. In combination with the large available bandwidth from 0.3-3THz this would enable high-speed communication and high-resolution imaging. However, few challenges need to be addressed to achieve such a goal. The radiated terahertz power and bandwidth from silicon devices are still limited, and the sensitivity of terahertz receivers can be further improved. This presentation will focus on the design challenges of terahertz signal generation, synthesizing and receiving terahertz frequencies well beyond silicon device limitations. It will cover the recent circuit realization in CMOS technology and novel generation and detection techniques.

CMOS technologies are enabling affordable and highly integrated solutions for Terahertz electronics. However, energy efficiency of CMOS Terahertz electronics is low and this must be improved to enable a wide range of applications including portable and small battery operated systems. The energy efficiency of CMOS techniques for signal generation and sensing at Terahertz will be reviewed. The efficiency of signal generation using N-push oscillators, transistor nonlinearity and reactive multipliers such as those based on Schottky diodes and accumulation MOS varactors will be compared. The circuit examples will include N-push circuits using QVCO’s, and 400 and 750 GHz frequency multipliers using symmetric MOS varactors. The energy efficiency of detectors and coherent detectors based on mixers in combination with local oscillators will also be discussed. LO signal generation poses the same challenge as signal generation. Use on an nth subharmonic mixer and its impact on energy efficiency will be described. Non-coherent detectors operating from 0.5-5 THz and a 410-GHz 4th subharmonic coherent detector APDP NMOS diode will be used for this discussion. Lastly, approaches for future investigation to improve the efficiency will be suggested.

In this presentation, we will review recent development of energy-efficient ultra-miniaturized THz radio systems in Silicon based platforms. Different modulation schemes and their impacts on system energy efficiency, data rate, and system complexity will be discussed. Silicon circuits and systems techniques to generate broadband high-power THz signals from low-frequency signals will also be presented, including a multi-phase sub-harmonic injection-locking scheme which generates a 500GHz signal from a GHz reference tone. As a design example, we will present a low-power ultra-miniaturized radio system that can support a two way communication at 350GHz. The system features transmitter/receiver circuitry reuse and asynchronous operation to ensure both low-power and ultra-compactness. Furthermore, the system includes co-design between the THz radio and the on-chip antenna to further reduce the system size and packaging complexity.

There is an increasing interest in low cost THz systems for medical imaging, spectroscopy, and high data rate communication. Recent results in the lower THz frequencies (

In this talk, we will discuss recent progress in the development of high-power multipliers above 200 Ghz. While several architectures are available for sub-Thz signal generation, broadband frequency multipliers provide a means to generate high-power over a very large bandwidth. Key to realizing efficient sub-Thz multipliers, is the system partitioning of frequency multiplication and power generation. We will discuss the tradeoffs and design methodologies as well as present an overview of the state of the art. Our talk will conclude with a discussion on the use of high-power multipliers in high-data rate communication in micro-scale radios.

Interfacing electronics directly with tissue has been realized in insects undergoing complete metamorphosis, by inserting electronics during intermediate metamorphosis stages. The tissue regeneration enables a reliable interface to nerves, muscles, and neurons. Insect cyborgs can therefore provide a platform to gather information using sensors and actuator optimized by millions of year of evolution. However, as in many wireless network technologies, a key challenge is the transfer of measured data and transmission to a receiver. Given the limited weight to be carried by insects, battery power and energy constraints are key challenges. This paper will describe the challenges and pose a few ideas to resolve the power issues. One set of solutions of communication power consumption is to implement phased arrays that focus energy in one direction to reduce power loss due to omnidirectional communications approaches. The phased arrays can be CMOS implemented RF or ultrasonic phased arrays such that information is targeted to receiving cyborgs in know direction in comparison to flying direction, much like guidance used by bees. This paper will present some results on GHz/MHz sonar chips that might implement low weight and low power directional communication links, and work in conjunction with RF radar circuits. These approaches would enable high fan-out directional message passing for forming multi-functional ad-hoc wireless flying networks.

Strongly correlated electron materials where many body interactions dominate single particle behavior exhibit collective carrier dynamics that, if properly harnessed, can enable novel functionalities and applications. In this talk, we demonstrate the phenomenon of electrical oscillations in a prototypical metal-insulator transition (MIT) system, vanadium dioxide (VO2). We show that the key to such oscillatory behavior is the ability to induce and stabilize a non-hysteretic and spontaneously reversible phase transition using a negative feedback mechanism. Further, we demonstrate the synchronization and coupling dynamics of such VO2 based highly compact relaxation oscillators and show, via experiment and simulation, that this coupled oscillator system exhibits rich non-linear dynamics including charge oscillations that are synchronized in both frequency and phase. Our approach of harnessing a non-hysteretic reversible phase transition region is applicable to other correlated systems exhibiting metal-insulator transitions and can be a potential candidate for applications in oscillator based non-Boolean computing and communication links for extremely miniaturized radios.

The advent of nonlinear vector network analyzers (NVNA) has been at the origin of the introduction of new paradigms in microwave engineering for both (1) the modeling of transistors and (2) the design of microwave power amplifiers. Circuit-based nonlinear microwave models can now be directly extracted from large-signal measurements for a targeted range of operation. Active load pull (ALP) measurements can be designed to replicate the typical mode of operation, temperature and trapping state of the transistor under various dynamic loading. The bias dependence of the charges and device IV characteristics can then be simultaneously extracted from a few large-signal measurements using artificial neural networks (ANN). Examples of SOS-MOSFET and GaN models extracted will be presented. Second NVNA’s find also application in the design of power amplifiers (PA). To optimize the power efficiency of PAs, optimal internal modes of operation are usually targeted at the internal device current-source reference planes. However a tremendously large search space for the multi-harmonic terminations must then be explored using loadpull for such waveform engineering. On the other hand if a nonlinear embedding device model is used, one can in a single simulation predict from the desired internal mode of operation, the required amplitude and phase of the multi-harmonic incident waves at the transistor measurement reference planes. Obviously this efficient PA design method is sensitive to the accuracy of the device model. Thus, NVNA measurements are warranted to verify that the deembedded data and the simulated results are consistent at the current source reference planes. Examples of such design for Doherty and Chireix amplifiers will be presented.

In this talk we focus on LSNA measurements, and in particular on characterization and modeling of microwave transistors. Ranging from low- to high-frequency, LSNA measurements provide a great deal of information which enable a comprehensive characterization and models improvement. We will show in particular the benefit of adding, in the characterization and modeling phases, low-frequency LSNA measurements in combination with high-frequency LSNA measurements. We will show modeling examples of GaAs and GaN transistors both for mixer and amplifier applications. Finally we discuss on how one can make directly use of LSNA measurements for the design of power amplifiers. In particular, different design examples will be shown, from quasi-linear to high-efficiency operation.

The presentation concerns the accurate description of a specific receiver to extract time domain RF waveforms at both ports of non linear devices. This receiver based on the use of THA is compared to other receivers used in other time-domain measurement equipment. It is also demonstrated the usefulness of this kind of receivers for the accurate characterization of non linear components, circuits or sub-systems for different civil or military applications as pulse to pulse characterization, doherty oriented power amplifier design and linearity improvement through large bandwith EVM measurements. Many results are presented to prove the capability of the whole measurement system in terms of Sampling frequency, dynamic and accuracy.

This work presents the use of a Nonlinear Vector Network Analyser (NVNA) measurement system in the development of GaN on Silicon from understanding and optimising the intrinsic device through to developing a 100 Watt plus packaged power amplifier and corresponding application circuit for 3G and 4G BTS applications. The NVNA measurement system is on-wafer enabling devices up to 15W peak power to be characterised and is based upon a Rhode & Schwarz 4-port ZVA-67 with a low-loss external test set. The measurement system is controlled via the Mesuro software and permits control of fundamental load, harmonic source or load impedances using active load-pull. In the development of the optimised GaN on Silicon process the NVNA is utilised in conjunction with pulsed DC-IV characterisation and analysis of the dynamic loadlines indicated that improvements could be made to the GaN on Silicon epi for optimal efficiency under 50V operation. The subsequent GaN on Silicon improvements increasing the peak efficiency performance tested on the NVNA with optimal harmonic impedances from 70% to 79% at the unit cell level. To translate this performance to the packaged power amplifier the unit cell is fully characterised using the NVNA with optimal fundamental and harmonic impedances characterised over the desired frequency of interest. It has been found that the 2nd harmonic input impedance plays a key role in achieving the desired performance, requiring in package terminations to realise. The fundamental and harmonic impedances collected from the NVNA being directly scaled to the larger device and translated through a package model, or the data is collected in a data-based model, Cardiff PHD model, permitting the package and application circuit designer to design within an EDA environment. Utilising the capabilities of the NVNA system, high power GaN on Si products are in development with efficiencies exceeding 70% at 2.7 GHz. Details of the device waveform analysis and subsequent use of the NVNA in the design flow would be presented.

The growing availability of modern large-signal microwave instruments, such as the NVNA and LSNA, have changed the landscape for active device characterization and modeling. This presentation will compare and contrast several very distinct approaches enabled by recent advances. Progress on scalable large-signal frequency domain behavioral X-parameter models for transistors will be reviewed. New device insight may be possible based on some of the consequences of this work, including the definition of new measurements that can potentially replace more familiar but less applicable linear figures of merit. Finally, identification of multiple timescale (electro-thermal, trapping and de-trapping) time-domain models from large-signal waveform data has become more practical with the introduction of some commercial tools and models. Recent advances in this area and future directions will be reviewed.

This lecture will present two NVNA measurements based applications. The first application is a simple methodology to observe the RF waveforms at the drain source current reference plane of the transistor, without using a complete nonlinear model. The aim is to allow Power Amplifier designers starting their work using VNA based harmonic and time domain load pull measurements, and S parameter measurements. The later measurements will be used to extract a linear model first. Then the parameters of the linear model will be used to deembed the load pull measurements directly at the voltage controlled current source plane, in order to enable waveform engineering. Because of the well know theoretic conditions that enable optimum efficiency, this methodology can also be used to avoid time consuming multi-harmonic load pull measurements. Harmonic impedances can be defined accordingly to the knowledge of the operating class addressed, while load pull optimization fundamental matching only. The second application is a new identification methodologies dedicated to packaged transistor behavioral modeling. Using the background of the Poly-Harmonic Distortion (PHD) model formalism, the extension of the model kernels description up to the third order makes the behavioral model more robust and accurate for a wide range of impedance loading conditions, which is a primordial when designing a High Power Added Efficiency Doherty Amplifier, where a load impedance variation can be observed as a function of the power level. In this paper, a model of a 15 W GaN Packaged Transistor has been extracted from Load Pull measurements for Class AB and Class C conditions. This new Enhanced PHD model (EPHD) and the original PHD model are benchmarked against Load Pull measurements in order to check the new formulation. An advanced validation at the circuit level was done in order to verify the ability of the EPHD model to predict the overall Doherty Amplifier performances.

Communication and radar signals have increased peak-to-average power ratios (PAPR) and bandwidths for efficient spectrum use, implying reduced transmitter average efficiency. Doherty, supply-modulated (ET) and outphasing transmitters offer possible efficiency improvements. This talk discusses various MMIC PA designs with 3 to 10W output power and peak PAE greater than 60% at X-band using the Qorvo 150-nm GaN process. Outphasing and Doherty PAs exhibit load modulation, and internal measurements of load modulation in several X-band PAs are presented. Furthermore, supply-modulated X-band transmitters with MMIC GaN dynamic, along with the simulation and measurement challenges for this type of transmitter, are discussed. At the University of Colorado, we have been researching advanced power amplifier and transmitter microwave architectures for improved energy and spectral efficiency. In this field, there is a need for nonlinear device and circuit characterization that is modular, lower cost and has additional functionality not available in existing measurement solutions. We are working on a large signal network analyzer (LSNA) which uses sub-samplers in time domain, using NI PXI instruments combined with specialized RF components in a dedicated LabVIEW framework. We have used a low-frequency version of the instrument, based on a NI platform, to characterize for the first time low-frequency signal-envelope (up to 500MHz) bandwidth complex drain supply port impedance of several GaN transistors and integrated amplifiers under large signal carrier operation. This knowledge allows us to design very efficient high-frequency dynamic supplies for envelope tracking. For example, we have demonstrated >10W output power at 10GHz with over 20dB saturated gain and 60% power-added efficiency combined with a >90% efficient 100-MHz switching power supply on the same GaN chip, enabled by specialized transistor characterization. At the carrier frequency (e.g. 10GHz), a similar preliminary system has allowed us to measure internal load modulation in an outphasing amplifier under supply modulation, as well as behavior of self-synchronous microwave power rectifiers. A combined high and low frequency version of this type of instrument will be presented. A brief discussion will be given in order to show what types of new design-oriented measurements can be performed using this type of powerful analysis.

Future wireless transmitters need to target improved energy efficiency while meeting strict linearity requirements. Some of the most promising solutions, based on Digital Doherty, outphasing, and varactor based load modulation architectures are founded on a combination of nonlinear RF and signal processing methods to reach this goal. We will in this presentation describe how the LSNA, when employed in various non-conventional setups, provides an essential tool in the development of these energy efficient and linear transmitter solutions.

Designing multi-functional, wideband and very efficient power amplifier systems under high PAR signals is a challenge. It is no longer adequate to perform just some source- and load-pull to find the optimal matching impedances. Envelope tracking techniques are being used to increase efficiency, digital predistortion is added to linearize the overall power amplifier system etc.. Due to the increased complexity of power amplifier systems it is very necessary to go back to the basics and understand the fundamental behaviors and characteristics of the amplifier in combination with its accessories which will lead to the performance of a complete power amplifier system. First the talk will give an overview of these fundamental behaviors and characteristics. Secondly one will discuss the type of measurements that are needed to provide these behaviors and characteristics in combination with the technical challenges. Finally a practical measurement system, based on vector signal analyzers, is explained and demonstrated that helps accelerating the design of high-efficiency power amplifiers where load-pull, envelope tracking, digital predistortion and design techniques meet each other.

RF integrated circuits are increasingly moving to higher frequencies with increased demand for linearity, power efficiency, size and weight, and overall system performance. In recent years, Si-based RF/mixed signal technologies have made remarkable progress by leveraging advanced technology nodes and integration density; however, compound semiconductor technologies still possess fundamental material property advantages. Heterogeneous integration is a promising technology to leverage both the material properties of compound semiconductors and the integration density of Si-based technologies in a single SoC. DARPA has invested in a number of programs to advance the design and manufacturing of RF solutions leveraging integrated III-V and advanced Si technology. This talk will discuss the latest advances achieved by these programs and their impact on RFIC design.

NGAS is developing a heterogeneous integration foundry through the DARPA DAHI program. The NGAS foundry processes allow for compact and flexible integration of InP HBT, GaN and GaAs HEMT, and high-Q passive technologies to advanced CMOS substrates. Recent progress on the foundry integration methods, processes design kits, and thermal analysis tools will be presented as well as recent advancements on internal heterogeneous integration efforts.

GaN devices are ideal for the high performance power amplifiers operating at frequencies which are unachievable with any silicon-only-based technology. Implementation of GaN technology on large diameter, thin Si wafers such as those required for CMOS (750 um for both 200 and 300 mm diameter) has been challenging due to large thermal and lattice mismatch issues. In this talk, we will demonstrate that these issues can be minimized by growing GaN on a patterned Si wafer and by proper engineering of the pattern dimensions and pattern density. This investigation is aimed at combining strength of both GaN and Si technologies by co-integrating GaN devices with Si integrated circuits for high power and high performance products.

We present our results on the successful wafer-scale, heterogeneous integration (HI) of GaN HEMTs and Si CMOS to create HI MMICs. Oxide bonding is being used to integrate GaN on 200 mm Si wafers with completed Si CMOS wafers. The HI MMIC process is being used to fabricate cost effective, high performance, digitally enhanced, RF and mixed signal ICs such as ‘intelligent’, highly-integrated transceivers.

Printing offers an excellent approach to making structures and devices using nanomaterials, however, current electronics and 3D printing using inkjet technology, used for printing low-end electronics are slow and provide only micro-scale resolution. The NSF Center for High-rate Nanomanufacturing (CHN) has developed a new fully automated system that uses directed assembly based printing at the nanoscale to make products that fully take advantage of the superior properties of nanomaterials. The Nanoscale Offset Printing System (NanoOPS) can print metals, insulators and semiconductors (including III-V and I-VI), organic and inorganic materials into nanoscale structures and circuits (down to 20 nanometers). The fully automated robotic cluster tool system prints at the nanoscale to make products that take full advantage of the superior properties of nanomaterials. The NanoOPS has been used to print utilizing the following nanomaterials: nanoparticles, nanotubes, nanowires, 2D materials and polymers. The center has many applications where the technology has been demonstrated. The center has developed many sensors, among them a biosensor chip (0.02 mm) capable of detecting multiple biomarkers simultaneously (in vitro and in vivo) with a detection limit that’s 200 times lower than current technology. In addition, the center made a printed Band-Aid sensor that could read glucose, urea and lactate levels using sweat. An inexpensive micro chemical sensor with a low detection limit that’s less than 1 mm in size has also been developed. The center has also 2D and 1D materials transistors and inverters and a CNT battery that can be fully charged in a few minutes and retain more 90% capacity.

We describe our development of a 3D heterogeneous integration platform to integrate Si CMOS with high-performance III-V devices. The technology utilizes Ziptronix direct bond interconnect (DBI™) technology for heterogeneous interconnects and wafer thinning with through-substrate vias to route I/O between layers. Device and circuit results from the integration of high performance InP HBTs with 130nm CMOS will be presented.

The wafer-level integration of InP DHBT onto SiGe BiCMOS enables the realization of analog mm- and sub-wave circuits with enhanced performance in terms of RF output power and bandwidth as compared to the SiGe-only technology. At the same time, the proven process maturity of BiCMOS can be leveraged to realize highly complex system-on-chip mm-wave RF front-ends, potentially displacing the costly and bulky traditional mm-wave co-packaging techniques. The heterointegration technology and realized complex mm-wave sources including a SiGe VCO and InP amplifier and multiplier, which cover an output frequency range from 160 to 325 GHz, will be presented. Access to the combined InP/SiGe technology in chip foundry mode will be described, including process design kit information.

Intimate device level heterogeneous integration using the DAHI process developed at Northrop Grumman Aerospace Systems (NGAS) enables integrated circuits to be designed using multiple transistor types for optimal performance. In this workshop, we will present the recent progress of a Q band frequency synthesizer using CMOS, InP and GaN technologies and integrated through DAHI. With the reconfigurability of the DAHI process developed at NGAS, this Q band frequency synthesizer can convert the signal to E band as well.

Raytheon is interested in E-band communications for high data rate throughput using small size, weight, and power communication systems. One specific example of the technology development efforts at Raytheon is the work we have done in the DARPA Mobile Hotspots (MHS) program. A simultaneous transmit and receive system with selectable polarization and beamwidth has demonstrated 1 Gbps data rates with our high power GaN amplifiers. Compact and broadband E-band high power amplifiers were developed support transmit modes with reflector antennas. A real-time rapid pull-in and tracking capability of the Raytheon gimbaled scan with the variable beamwidth antenna was also demonstrated in the MHS program. Measured results of this technology will be discussed

As end user consumption of data continues to soar unabated, increasing strain is placed on the fronthaul and backhaul networks to transport the ever increasing traffic. The incumbent solutions, typically microwave Point-to-point links in the 6 to 43GHz bands, have provided adequate capacity but increasingly, operators are looking to millimeter wave, generally, and E-Band, in particular, with the abundant available spectrum and favorable spectrum licensing regulations. With 10GHz of total available spectrum from lower, 71 to 76GHz, and upper, 81 to 86GHz, bands, even with modest spectral efficiency, E-Band can deliver many benefits to operators, such as, fewer radio variants, smaller antenna size, lower licensing fees. However, with increasing popularity and desire to increase network density, pressure is already mounting for higher performance solutions that offer improved spectral efficiency. In this talk, the motivation for high capacity millimeter wave radio links will be introduced and the circuit design challenges inherent in optimizing total network capacity with high throughput radio links using high order modulations, such as 1024QAM, at very high frequencies will be discussed.

E band communications with its large available spectrum allocations was brought in use about 10 years ago. Despite the available spectrum, utilization of this band has been slower than some of the lower frequency slots. Part of the problem is cost and the other is the performance limitations of the communication hardware. Recent advances in short gate CMOS technologies may alleviate the cost side of the equation. The MMIC performance ( heretofore accomplished with GaAs) has been limited. NGAs has been maturing technologies that will bring boost the dynamic range of the E band links and help fill the data pipeline. Whether it is our legacy 0.1um GaAs coupled with 0.1um InP front end amplifiers for excellent Noise Figures and or the high power and highly linear GaN Pa’s and drivers, NGAS’s semiconductor technology offers un-matched performance without the high price tag. We will summarize the offerings and show roadmaps to our next generation chipsets.

Silicon based E-band radio systems offer high integration level and dramatically reduce the system production cost, however, they suffer from low performance issues, such as limited linearity, high phase noise, high noise figure, and low output power. Recently, we demonstrated fully-integrated high-performance SiGe based transceiver chipset, which includes receiver and transmitter in a double conversion superhetrodyne sliding–IF architecture, that covers both lower and higher bands, and allows full duplex throughput required to utilize the full potential of the E-band standard. In this talk, the transceiver architecture as well as the design considerations for meeting the challenges of the regulatory requirements, such as spectrum emission masks, dynamic range, and interferer immunity, will be analyzed. In addition, a set of circuit components that compose our fully-integrated E-band chipset will be reviewed. The components performance and topology were derived from the above constrains. Finally, the chipset measured performance will be presented.

To date, GaAs High Electron Mobility Transistor (HEMT) is the most used and established technology for mm-wave MMICs due to its satisfactory high frequency performance. The reliability, stable manufacturing, performance and pricing of GaAs are very competitive, which make this technology very attractive for commercial use. Gotmic has over the years developed a wide range of high performance MMIC products using commercial foundries. Today these circuits are used in several E-band and related mm-wave systems. This presentation will cover topics such as circuit performance, design, price and integration on MMIC/package level. Furthermore we will address the market and future outlook for the E-band.

E-band (70/80GHz) has worldwide availability, is mostly light licensed, interference free, has much wider channel bandwidths (250 MHz and above) available and also low oxygen absorption, allowing much longer hops. Wireless links can be deployed quite quickly compared to optical fiber and also now the technology exists it makes the total cost of ownership of the point-to-point radio link lower than optical fiber. A number of IC manufacturers have developed chip sets for E-Band transceivers, some in Silicon and others in GaAs. Infineon's mm-wave transceiver product family allows one to send >1 GB/s data rates over a wireless mm-wave link. Infineon's RF expertise and technology capability enable more applications such as Radar and Sensing. Infineon´s own fabricated SiGe technologies is used to realize cost-optimised and integrated packaged single chip mm-wave transceivers. By co-developing the chip and package using eWLB (embedded Wafer-Level Ball Grid Array), Infineon realizes a compact design in a plastic housing. This presentation will discuss the radio link design and performance that can be achieved at E-Band with a front-end design using Infineon SiGe transceivers including the following topics: - E-BAND MARKET VIEW and OUTLOOK - E-BAND TRANSCEIVER and FRONT-END-MODULES - EVALUATION BOARD FOR E-BAND FRONT-END-MODULE - FRONT-END-MODULE PERFORMANCE - CONCLUSION

Multi-layered and three-dimensional MMIC (3-D MMIC) researches were carried out in the 1990's, while there were many twists and turns in/after the era. We launched a novel wafer-level chip size (scale) package (WLCSP) technology by aggressively modifying the 3-D MMIC technology in 2008. The WLCSP currently employs 0.1um-gate AlGaAs/GaAs PHEMTs and is designed to be flip-chip assembled as an excellent platform at all frequencies from 10 GHz to 100 GHz. No package is necessary for practical use, achieving low cost. Some applications of the WLCSP technology to the 77 GHz automotive radars and the 80 GHz-band (E-band) communication transceivers, as well as point-to-point communication transceivers (several bands in 13-42 GHz), will be presented.

The popularity of multimedia applications and broadband internet has created an ever increasing demand for achieving higher throughputs in cellular and wireless networks. Thus far, microwave (up to 43GHz) wireless point-to-point links have been playing an important role in carrying a large portion of this data by interconnecting cellular base stations or enterprise buildings. There is continuing exponential growth of subscriber throughout the world and ODU vendors are looking for solution that can help to upgrade to next generation cellular networks that supports throughput comparable to fiber-optic links (Gbps) at low cost with fast deployment. E-band based network are very attractive for such multi-Gigabit per second (Gbps) wireless links due to availability of 10GHz spectrum in the 70 and 80 GHz band. Gigoptix is working on a complete Tx/Rx chip set solution employing various technologies such as GaAs and SiGe in a SiP (system in package). This approach provides the best of GaAs and SiGe technology performance for Tx and Rx in a SiP, thus the developed solution can handle a complex modulation scheme such as 64QAM with 1GHz bandwidth. This presentation will discuss about various IC technologies available for E-band such as GaAs/GaN and SiGe and their tradeoffs for various circuit design such as Power Amplifier, Mixer, and LNA etc for developing an E-band Transceiver chipset. In addition to chipset development at MMIC level, some aspect of low cost and high performance of packaging such as SiP will also be covered.

One way of evaluating the features of a PDN is by observing the impedance profile as seen by the pads on the die. This will always show parallel resonance between capacitive elements and inductive elements. In many systems, the largest peaks are from the on-die capacitance and package lead inductance. This is called the Bandini Mountain. It is often the source of system failures. In this presentation the features of the Bandini Mountain will be reviewed and some recommendations of how to fix it at the semiconductor, the package, the board and the system architecture level will be introduced.

A great deal of emphasis is being placed on the operating efficiency and size reduction of today's Voltage Regulator Modules (VRMs), and in part new eGan technology is providing a solution path. VRMs are also gravitating towards all ceramic output capacitor solutions to meet the demand for size reduction. A common byproduct of all ceramic decoupling capacitor solutions is a less than flat VRM output impedance.In this session we will look at how system performance is degraded by a non-flat VRM impedance. We will show how to design, simulate and measure the VRM impedance as well as how to optimally implement external capacitor series resistance to allow an all ceramic capacitor solution for a small footprint high efficiency designs.

Today’s Field Programmable Gate Arrays (FPGA) have many high speed gigabit i/o lines that transmit digital data with rise times of 10s of picoseconds. The transceiver architectures that create the best quality communications employ many advanced features that ensure proper functionality over many years of operation. One aspect of this FPGA design that has become challenging is the power distribution network (PDN) that power these advanced circuits internal to the FPGA chip itself. Standard CMOS power supply designs of the past have traditionally required their own power plane and ground plane design rules, however, these new breed of FPGA transceiver PDNs have new design challenges not typically encountered. Inductance of power plane cut-outs, suppression of huge switching currents, and advanced decoupling techniques on the die and in the package pose require a new way to think about PDN desgin. Controlling transients in the picosecond regime reducing noise to single digit millivolts at low frequencies requires fastidious attention to power delivery details. This presentation will provide the background and guidance for designing an effective PDN for these circuits.